1. Field Of the Invention
The present invention relates to a time-division multiplex transmission network system in which data having a predetermined number of bits can be transferred between a great number of data transmitters and data receivers in a time division mode with a high efficiency and high reliability and without generation of high-frequency noise on signal transmission lines.
2. Description Of the Prior Art
Conventional network systems are exemplified by a Japanese Patent Application Examined Open No. Sho. 52-13367.
The network system disclosed in Japanese Patent Application Examined Open No. Sho. 52-13367 comprises a plurality of data transmission stations and data reception stations, these data stations being interconnected via a synchronizing signal transmission line and data transmission line, and a synchronizing signal generator which generates and sends a synchronizing signal to each data station via the synchronizing signal transmission line. The synchronizing signal generator generates the synchronizing signal such that a level change in an M-series code signal repeating an order of H, H, L, L, H, and L at a constant interval T is modulated in a pulse width modulation method by means of a clock signal having a period of .tau..
On the other hand, each data transmission station comprises: a reception circuit which receives the synchronizing signal from the synchronizing signal generator and demodulates the received synchronizing signal into the clock signal and the M-series code signal; a multi-bit shift register which shifts sequentially the demodulated code signal in synchronization with the clock signal; and a logic gate circuit which opens the gate when the output of each stage of the shift register is logically calculated and gives a predetermined logic result. A combination logic pattern of "H" and "L" levels of the shift register appears seven kinds during one period of the M-series code signal. Therefore, if any one of the seven kinds of combination pattern is selected as an establishment condition of the logic gate circuit, the gate thereof is opened only once during the one interval of the M-series code signal so that a data output circuit outputs one bit of data to the data transmission line.
Similarly, each data reception circuit is so constructed that when a predetermined logic combination pattern appears during the one interval of the M-series code signal, a gate thereof is opened so that one bit of data can be received. In this way, data transmission and reception between one of the data transmission stations and one of the data reception stations which has the same gate opening logic condition as the data transmission station becomes possible so that the data transmission and reception can be carried out without collision of data which is transmitted and received between any othere data stations.
On the other hand, there is a demand in a general network system that a parity bit is added to an on-and-off information on such as a switch or an information on such as level intensity or switching timing in addition to the above-described on-and-off information is transmitted as data having a plurality of bits. In this case, if such a data is transmitted using the above-described conventional network system, the data must be transmitted by one bit whenever the address coincidence occurs, i.e., a plural numbers of times the address coincidence must be carried out to transmit a single data so that a longer time of data transmission is required.
Another network system which improves the above-described network system has been proposed in a Japanese Patent Application Unexamined Open No. Sho. 59-230348 published on Dec. 24, 1984.
In the network system disclosed in the Japanese Patent Application Unexamined Open No. Sho. 59-230348 (U.S. application Ser. No. 592,547 filed on Mar. 23, 1984 now pending), once an address derived from the synchronizing signal accords with that specified to one of the data transmission stations and one of the data reception stations between which data having a plurality of bits are to be transmitted and received, the data having the plurality of bits can be transmitted and received at one time in a pulse-width modulation method.
Since in the later conventional network system the data having, e.g., four bits can be transmitted within a reference time of the synchronizing signal having a frequency of, e.g., 512 Hz, the data transmission can be carried out at a higher speed. Since it is possible to include the parity bit in the four bits, the reliability of data transmission can accordingly be improved.
However, although it is desirable for a network system which can transmit wholly data comprising multiple bits more than four bits at a high speed to extend its application fields, the network system disclosed in the latter Japanese Patent Application may result in a generation of high frequency noise due to excessively high transmission frequency in its data transmission line.